This invention is in the field of microprocessor and other integrated logic circuits, and is more specifically directed to fault detection circuitry therein.
A common function performed by conventional microprocessors in preparing an instruction for execution is referred to as fault detection. Fault detection, in general, determines whether a register or memory location is available for use in connection with the instruction. For example, a read fault occurs if an instruction that is about to be executed (or, in simple cases, is being executed) includes a read of data from a register or memory location that does not contain valid data; conversely, a write fault occurs if an instruction includes a write of data to a register or memory location that is already in use (i.e., contains valid data from a different operation). In the event that a fault is detected, the fault detection circuitry may issue an exception, causing the microprocessor to process certain control operations to dear the exception.
Fault detection is especially important in microprocessors of the pipelined type, in which multiple instructions are processed simultaneously along various stages of execution. The effective rate at which instructions are executed by a pipelined microprocessor can approach one instruction per machine cycle per pipeline, even though the processing of each individual instruction may require multiple machine cycles from fetch through execution. In a pipelined microprocessor, fault detection is typically performed during the scheduling pipeline stage, so that an instruction involving a read or write fault is not issued to execution. Fault detection may be performed not only relative to previously executed and completed instructions, but also relative to instructions that are not yet executed but which are further along in the pipeline. Handling of faults in pipelined microprocessors generally involves the flushing and refilling of the pipeline, and thus involve significant delay.
According to prior techniques, fault detection is performed in a relatively simple manner by straightforward logic. Attention is directed, in this regard, to FIG. 1, which illustrates conventional fault detection logic, as is typically implemented into the scheduling circuitry of the microprocessor. In this conventional arrangement, write fault detection is being performed upon an instruction that includes a three-bit address indicating one of eight possible registers to which a write is to be effected upon execution of the instruction. Selection information, such as register and memory addresses, are typically contained within instructions in encoded form, to save word width and thus chip area. In the conventional fault detection logic of FIG. 1, the register address is communicated on three lines REGADR to the input of 3:8 decoder 2 which, in turn, drives one of eight output lines SEL to an active state in response to the address on lines REGADR. Lines SEL from decoder 2 are applied to inputs of AND function 4. Mask register M, according to this conventional arrangement, includes eight bit positions M.sub.0 through M.sub.7 corresponding to the eight registers; each of bit positions M.sub.0 through M.sub.7 indicate, when set, that its corresponding register contains valid data, such that the execution of a write thereto would constitute a write fault. State or condition information, such as the valid data information stored in bit positions M.sub.0 through M.sub.7 of mask register M, is generally stored in decoded form, to eliminate the need for decoder circuitry and considering that the extent to which the state information is to be communicated within the integrated circuit is relatively small. The contents of mask register M are also applied to inputs of AND function 4.
AND function 4 performs eight bit-by-bit logical AND operations between each of lines SEL from decoder 2 and a corresponding one of the bit positions M.sub.0 through M.sub.7 communicated thereto; as such, AND function 4 has eight outputs, on lines CHECK, at which the results of the eight logical ANDs are presented. In this example, assuming active and set states are at a high logic level, AND function 4 will drive a high logic level at one of lines CHECK if the register location addressed by the instruction under test (as indicated by lines REGADR) already contains valid data (as indicated by the corresponding one of bit positions M.sub.0 through M.sub.7 of mask register M). The states of lines CHECK from the output of AND function 4 are combined by OR function 6 to drive line FLT that indicates, when high, that a write fault is detected.
The conventional logic of FIG. 1 is thus operable to detect write faults in microprocessor instructions; similar logic will also be used to detect read faults, in which case the fault will be indicated if the addressed register does not contain valid data. In either case, significant delay is encountered in this conventional logic realization of the fault detection logic. For example, 3:8 decoder 2 is generally realized with a gate depth of three, and eight-input OR function 6 is generally realized with a gate depth of two. As such, the overall gate depth of the conventional logic realization of FIG. 1 is about six, considering one gate delay for AND function 4.
While six gate delays may be considered to be insignificant in modern VLSI microprocessors, it has been observed, in connection with the present invention, that fault detection may be part of a critical path in the instruction flow, such that any additional delay in fault detection directly affects the microprocessor performance. For example, fault detection performance has been observed to be particularly critical in the performance of on-chip floating-point units (FPU), where the performance of the microprocessor in executing complex computational routines is directly affected by the time required for scheduling of instructions, particularly in the repetitive instruction loops often encountered in floating-point computational routines.